module dec68a title 'address decoder for 68k computer' dec68a device 'P22V10'; clk pin 1; as pin 2; a23 pin 3; a22 pin 4; a21 pin 5; a20 pin 6; uds pin 7; lds pin 8; rw pin 9; uwe pin 23 istype 'com, invert'; lwe pin 22 istype 'com, invert'; uoe pin 21 istype 'com, invert'; loe pin 20 istype 'com, invert'; ram pin 19 istype 'com, invert'; rom pin 18 istype 'com, invert'; dev pin 17 istype 'com, invert'; dev68 pin 16 istype 'com, invert'; devint pin 15 istype 'com, invert'; addr = [ a23, a22, a21, a20 ]; rom_addr = ^h0; " ROM address ram_addr = ^h1; " RAM address devint_addr= ^hd; " Intel style peripheral address dev_addr = ^he; " 68k peripheral address dev68_addr = ^hf; " 6800 peripheral address H,L,X = 1,0,.X.; equations !ram = !as & (addr == ram_addr); !rom = !as & (addr == rom_addr); !dev68 = !as & (addr == dev68_addr); !dev = !as & (addr == dev_addr); !devint = !as & (addr == devint_addr); !uwe = !as & !rw & !uds; !lwe = !as & !rw & !lds; !uoe = !as & rw & !uds; !loe = !as & rw & !lds; ram.oe = 1; rom.oe = 1; dev68.oe = 1; dev.oe = 1; devint.oe = 1; uwe.oe = 1; lwe.oe = 1; uoe.oe = 1; loe.oe = 1; test_vectors ( [ as, addr ] -> [ rom, ram, dev, dev68, devint ] ) [ H, X ] -> [ H, H, H, H, H ]; [ L, ^h0 ] -> [ L, H, H, H, H ]; [ L, ^h1 ] -> [ H, L, H, H, H ]; [ L, ^h2 ] -> [ H, H, H, H, H ]; [ L, ^h3 ] -> [ H, H, H, H, H ]; [ L, ^h4 ] -> [ H, H, H, H, H ]; [ L, ^h5 ] -> [ H, H, H, H, H ]; [ L, ^h6 ] -> [ H, H, H, H, H ]; [ L, ^h7 ] -> [ H, H, H, H, H ]; [ L, ^h8 ] -> [ H, H, H, H, H ]; [ L, ^h9 ] -> [ H, H, H, H, H ]; [ L, ^ha ] -> [ H, H, H, H, H ]; [ L, ^hb ] -> [ H, H, H, H, H ]; [ L, ^hc ] -> [ H, H, H, H, H ]; [ L, ^hd ] -> [ H, H, H, H, L ]; [ L, ^he ] -> [ H, H, L, H, H ]; [ L, ^hf ] -> [ H, H, H, L, H ]; test_vectors ( [ as, rw, uds, lds ] -> [ uwe, lwe, uoe, loe ] ) [ H, X, X, X ] -> [ H, H, H, H ]; [ L, H, L, H ] -> [ H, H, L, H ]; [ L, H, H, L ] -> [ H, H, H, L ]; [ L, H, L, L ] -> [ H, H, L, L ]; [ L, H, H, H ] -> [ H, H, H, H ]; [ L, L, L, H ] -> [ L, H, H, H ]; [ L, L, H, L ] -> [ H, L, H, H ]; [ L, L, L, L ] -> [ L, L, H, H ]; [ L, L, H, H ] -> [ H, H, H, H ]; end dec68a