VC8/I Implimentation using Flip-Chips C H Dickman - Spring 2005 - updated 2008-3-18 The following describes a PDP8 Positive I/O Bus implementation of the VC8/I using a KA8/E and a bunch of Flip-Chips. The light pen interface is NOT implemented. IOT's 6051 clear X register 6052 load X register 6054 display point at XY 6061 clear Y register 6062 load Y register 6064 display point at XY 6075 load brightness register with intensity 1 6076 load brightness register with intensity 2 6077 load brightness register with intensity 3 Adjustments -Vrx: Turn trimpot on A08 (A702) so that B07R2 is -10vdc. -Vry: Turn trimpot on A10 (A702) so that B09R2 is -10vdc. Delay: Adjust trimpot on B11 (M306) so that A11A1 and A11D1 have settled to a final value before A11L2 (beam intensity) begins to fall. Falling beam intensity means the dot is getting brighter. Duration: Adjust trimpot on B12 (M306) so that the brightness of the beam is correct. Module Utilization Diagram Row B Row A +---------------+---------------+ | M953 (BAC) | M953 (BAC) | Slot 01 | +---------------+---------------+ | | M953 (BMB) | M953 (BMB) | Slot 02 | Row A connects to KA8-E +---------------+---------------+ | Row B chains to next Posi Bus | M953 (AC) | M953 (AC) | Slot 03 | +---------------+---------------+ | M103 (IOT5) | M101 (BAC L) | Slot 04 +---------------+---------------+ | M103 (IOT6) | M111 (BAC) | Slot 05 +---------------+---------------+ | (oops) | M206 | Slot 06 | Row B must be empty to allow + +---------------+ | space for A618 | A618 (X) | Slot 07 +---------------+---------------+ | | A702 (-10VRX) | Slot 08 | Row B must be empty to allow + +---------------+ | space for A618 | A618 (Y) | Slot 09 +---------------+---------------+ | M103 (IOT7) | A702 (-10VRY) | Slot 10 +---------------+---------------+ | M306 (DLY) | M921 | Slot 11 | Row A acts as output and PS termination +---------------+---------------+ | M306 (DUR) | M113 | Slot 12 +---------------+---------------+ | | | Power Requirements +5 +15 -15 -vr A618 135 25 85 60 mA A618 135 25 85 60 A702 25 100 A702 25 100 M101 82 M103 110 M103 110 M103 110 M111 87 M113 71 M206 87 M306 120 M306 120 ---- ---- ---- ---- 1167 115 385 120 mA Board Modifications 1. Install .001 uF capacitor between L2 and M2 on B11 (M306). 2. Install .001 uF capacitor between L2 and M2 on B12 (M306). Wire Run List Note: There was a mistake in the intial layout that required moving the M103 in B06 to B10. The following run list includes this oops. BMB03(0) A02H1 B04D2 B05D2 B06D2 B10D2 BMB04(0) A02L1 B04E2 B05E2 B06E2 B10E2 BMB05(0) A02P1 B04F2 B05F2 B06F2 B10F2 BMB06(1) A02E2 B04H2 B05H2 B06H2 B10H2 BMB07(0) A02H2 B04J2 BMB07(1) A02K2 B05J2 B06J2 B10J2 BMB08(0) A02M2 B05K2 BMB08(1) A02P2 B04K2 B06K2 B10K2 BMB10(1) A02T2 A04C1 A06C1 BMB11(1) A02V2 A06J1 BIOP1 A01K2 B04P2 B05P2 B06P2 B10P2 BIOP2 A01M2 B04R2 B05R2 B06R2 B10R2 BIOP4 A01P2 B04S2 B05S2 B06S2 B10S2 CLEAR X L B04B1 B04H1 LOAD X L B04D1 B04J1 CLOCK X B04K1 B07N2 A07D2 DIS X L B04F1 B04L1 CLEAR Y L B05B1 B05H1 LOAD Y L B05D1 B05J1 CLOCK Y B05K1 B09N2 A09D2 DIS Y L B05F1 B04M1 DISPLAY B04N1 B11H2 B12H2 DELAY RES B11D2 B11E2 HIGH B11J2 B11K2 DELAY PULSE L B11S2 A12T2 DISP RES B12D2 B12E2 HIGH B12J2 B12K2 BR PULSE B12T2 A12U2 B INITIALIZE A01V2 A05M2 INIT L A05N2 A06D1 A06K1 BR CLOCK B10E1 B06E1 A06B1 A06H1 BR0 (1) A06E1 A12H1 A12L2 BR0 (0) A06F1 A12A1 BR1 (1) A06L1 A12B1 A12M2 BR1 (0) A06M1 A12J1 INT1 L A12C1 A12D1 A12E1 INT1 A12F1 A12D2 INT1 PULSE L A12F2 A11P1 INT2 L A12K1 A12H2 A12J2 INT2 A12K2 A12L1 INT2 PULSE L A12N1 A11R1 INT3 L A12N2 A12P1 A12R1 INT3 A12S1 A12P2 INT3 PULSE L A12S2 A11S1 DISP PULSE L A12V2 A05S2 DISP PULSE A05T2 A12E2 A12M1 A12R2 BAC02 A01E1 A04A1 BAC03 A01H1 A04D1 BAC04 A01J1 A04E2 BAC05 A01L1 A04F1 BAC06 A01M1 A04H2 BAC07 A01P1 A04J1 BAC08 A01S1 A04K2 BAC09 A01D2 A04L1 BAC10 A01E2 A04M2 BAC11 A01H2 A04N1 BAC02 L A04B1 A05A1 BAC03 L A04E1 A05C1 BAC04 L A04F2 A05D1 BAC05 L A04H1 A05F1 BAC06 L A04J2 A05E2 BAC07 L A04K1 A05J1 BAC08 L A04L2 A05H2 BAC09 L A04M1 A05L1 BAC10 L A04N2 A05K2 BAC11 L A04P1 A05N1 BBAC02 A05B1 A07E2 A09E2 BBAC03 A05D2 A07F2 A09F2 BBAC04 A05E1 A07M2 A09M2 BBAC05 A05H1 A07N2 A09N2 BBAC06 A05F2 A07S2 A09S2 BBAC07 A05K1 A07T2 A09T2 BBAC08 A05J2 B07D2 B09D2 BBAC09 A05M1 B07E2 B09E2 BBAC10 A05L2 B07H2 B09H2 BBAC11 A05P1 B07J2 B09J2 ANX A11A1 B07S2 ANY A11D1 B09S2 ANZ A11L2 +5 A11A2 A11K1 +15 A11T2 B07V2 B09V2 GND B07T2 B09T2 B09T1 -10REFX A08E2 B07R2 -10REFY A10E2 B09R2 -15 A11V1 B07U2 A07B2 B09U2 A09B2 A08B2 A10B2 Testing Code Test 1 clear x register 0200 6051 DCX 0201 7000 NOP 0202 7000 NOP 0203 5200 JMP 0 Signal Checks B04V2 should be true (HI) during the IOT BO4A1 should pulse true (HI) during IOT05 IOP1 BO4B1 should pulse true (LO) during IOT05 IOP1 Test 2 cycle through instructions 0200 6051 DCX 0201 6052 DLX 0202 6054 DSP 0203 6061 DCY 0204 6062 DLY 0205 6064 DSP 0206 6077 DBR 3 0207 6076 DBR 2 0210 6075 DBR 1 0211 5200 JMP 0 Signal Checks Examine IOP for each instruction Test 3 settling time 0200 7200 CLA 0201 1220 TAD 020 0202 6052 DLX 0203 6066 DLY DSP 0204 7040 CMA 0205 3220 DCA 020 0206 1221 TAD 021 0207 3222 DCA 022 0210 2222 ISZ 022 0211 5210 JMP 0010 0212 5201 JMP 0001 0220 0000 0221 7766 Test 4 Z axis test 0200 6077 DBR 3 0201 6054 DSP 0202 6076 DBR 2 0203 6064 DSP 0204 6075 DBR 1 0205 6064 DSP 0206 5200 JMP 0